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FEATURES

LT3487 Boost and Inverting Switching Regulator for CCD Bias DESCRIPTIO
The LT(R)3487 dual channel switching regulator generates positive and negative outputs for biasing CCD imagers. The device delivers up to -8V at 90mA and 15V at 45mA from a lithium-ion cell, providing bias for many popular CCD imagers. The boost regulator incorporates output disconnect technology to eliminate the DC current path from VIN to the output load that is present in standard boost configurations. The 2MHz switching frequency allows CCD solutions using tiny, low profile capacitors and inductors and generates low noise outputs that are easy to filter. Schottky diodes are internal and the output voltages are set with one resistor per channel, reducing the external component count. Intelligent soft-start allows sequential soft-start of the two channels with a single capacitor. The soft-start is sequenced such that the output ramp of the negative channel begins after the ramp of the positive channel. Internal sequencing circuitry also disables the negative channel until the positive channel has reached 87% of its final value, ensuring that the sum of the two outputs is always positive. The LT3487 is available in a 10-pin 3mm x 3mm DFN package.
Generates 15V at 45mA, -8V at 90mA from a Li-Ion Cell Output Disconnect Sequencing: Positive Output Reaches Regulation Before Negative Channel Begins Switching Internal Schottky Diodes 2MHz Constant Switching Frequency Requires Only One Resistor per Channel to Set Output Voltages VIN Range: 2.3V to 16V Output Voltage Up to 28V Short-Circuit Robust Capacitor Programmable Soft-Start Separate VBAT Pin Allows Separate Sources for Power and Control Circuitry Available in 10-Lead (3mm x 3mm) DFN Package
APPLICATIO S

CCD Bias TFT LCD Bias OLED Bias Rail Generation for Op Amps
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATIO
2.2F VIN 3V TO 12V 1F DN 47pF 15H VNEG -8V 90mA 22F FBN 324k RUN/SS 100nF RUN/SS SWN VIN
15H
10H
VBAT
SWP 70 EFFICIENCY (%) CAP 549k FBP 4.7F 100nF 65 60 55 50 VPOS VPOS 15V 45mA 45 40 VIN = 3.6V 0 20 80 60 LOAD CURRENT (mA) 40 100
3487 TA01b
LT3487
GND
3487 TA01a
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Conversion Efficiency
80 75 POS CHANNEL AT CAP
POS CHANNEL AT VPOS NEG CHANNEL
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LT3487 ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW CAP SWP VBAT SWN DN 1 2 3 4 5 11 10 VPOS 9 FBP 8 RUN/SS 7 FBN 6 VIN
VIN Voltage ............................................................... 16V VBAT Voltage ............................................................. 16V SWP, SWN Voltage................................................... 32V CAP, VPOS .................................................................30V DN Voltage ............................................................. -32V RUN/SS Voltage ..........................................................8V FBP Voltage................................................................ 6V FBN Voltage ................................................ -0.2V to 6V Maximum Junction Temperature .......................... 125C Operating Temperature Range ................. -40C to 85C Storage Temperature Range................... -65C to 125C
DD PACKAGE 10-LEAD (3mm x 3mm) PLASTIC DFN JA = 43C/W, JC = 3C/W EXPOSED PAD (PIN 11) IS GND, MUST BE CONNECTED TO PCB
ORDER PART NUMBER LT3487EDD
DD PART MARKING LBXB
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges.
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 3.6V, VBAT = 3.6V, unless otherwise noted.
PARAMETER Operating Voltage Range Quiescent Current RUN/SS Voltage Threshold (Full Current) RUN/SS Voltage Threshold (Shutdown) RUN/SS Pin Current FBP (Positive Channel) Pin Voltage FBN (Negative Channel) Pin Voltage FBP Pin Voltage Line Regulation FBN Pin Voltage Line Regulation FBP Pin Bias Current FBN Pin Bias Current FBP Threshold (Percent of Final Value) to Start Negative Channel Switching Frequency Maximum Duty Cycle Positive Channel Switch Current Limit Negative Channel Switch Current Limit Positive Channel VCESAT Negative Channel VCESAT (Note 5) (Note 5) ISWP = 400mA ISWN = 600mA

ELECTRICAL CHARACTERISTICS
CONDITIONS RUN/SS = 3V, Not Switching RUN/SS = 0V (Note 3)
MIN 2.3
TYP 3.7 5.3
MAX 16 5 8 1.6
UNITS V mA A V mV A V mV %/V mV/V
100 1 1.19 -7
160 1.4 1.23 3 0.007 0.001 2 1.27 12
RUN/SS = 0V (Note 4)

24.4 24.4
25 25 87
25.6 25.6 90 2.15
1.85 87 750 900
2 93 920 1090 280 340
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A A % MHz % mA mA mV mV
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LT3487 ELECTRICAL CHARACTERISTICS
PARAMETER Schottky DP Forward Drop Schottky DN Forward Drop Disconnect PNP VCE Disconnect Current Limit VCAP - VBAT to Disconnect Disconnect Leakage
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 3.6V, VBAT = 3.6V, unless otherwise noted.
CONDITIONS ISWP = 400mA ISWN = 600mA IVPOS = 50mA VCAP = 15V, VPOS = 0V VBAT = 3.6V, VPOS = 0V, ICAP < 100A VBAT = 3.6V, CAP = 3.6V, VPOS = 0V 100 MIN TYP 1045 980 205 155 1.2 0.1 1.6 1.0 MAX UNITS mV mV mV mA V A
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3487E is guaranteed to meet specified performance from 0C to 85C. Specifications over the -40C to 85C operating range are assured by design, characterization and correlation with statistical process controls.
Note 3: Guaranteed by design, not directly tested. Note 4: Current flows out of pin. Note 5: Current limit guaranteed by design and/or correlation to static test. Slope compensation reduces current limit at higher duty cycle.
TYPICAL PERFOR A CE CHARACTERISTICS
Shutdown Quiescent Current
10 PERCENTAGE OF FINAL FBP VOLTAGE (%) 100
QUIESCENT CURRENT (A)
8
4
70
2
60
0 -50
-25
50 25 0 75 TEMPERATURE (C)
100
125
50 -50
-25
50 25 0 75 TEMPERATURE (C)
100
125
VFBP (V)
6
UW
3487 G01
Positive Output to Enable Inverter
1.300
FBP Voltage
90 1.275 80
1.250
1.225
1.200 -50
-25
75 0 25 50 TEMPERATURE (C)
100
125
3487 G02
3487 G03
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LT3487 TYPICAL PERFOR A CE CHARACTERISTICS
FBN Voltage
10.0 7.5 5.0 VFBN (mV) 2.5 0 -2.5 -5.0 -7.5 -10.0 -50 -25 0 50 75 25 TEMPERATURE (C) 100 125 24.0 -50 24.0 -50 24.5 24.5 IFBP (A) IFBN (A) 25.0 25.0 25.5 25.5 26.0
Positive Channel Switch VCE(SAT)
NEGATIVE SWITCH SATURATION VOLTAGE (mV) POSITIVE SWITCH SATURATION VOLTAGE (mV) 500 500
POSITIVE SCHOTTKY FORWARD CURRENT (mA)
400
300
200
100
0
0
100
200 300 400 500 SWITCH CURRENT (mA)
Negative Channel Schottky I-V Characteristic
NEGATIVE SCHOTTKY FORWARD CURRENT (mA) 800 700 600 500 400 300 200 100 0 600 650 700 750 800 850 900 950 1000 SCHOTTKY FORWARD DROP (mV)
3487 G10
VCAP - VPOS (mV)
ICAP (mA)
4
UW
3487 G04
FBP Bias Current
26.0
FBN Bias Current
-25
75 0 25 50 TEMPERATURE (C)
100
125
-25
75 0 25 50 TEMPERATURE (C)
100
125
3487 G05
3487 G06
Negative Channel Switch VCE(SAT)
600 500 400 300 200 100
Positive Channel Schottky I-V Characteristic
400
300
200
100
0 0 100 200 300 400 500 600 700 800 900 SWITCH CURRENT (mA)
3487 G08
600
0 600 650 700 750 800 850 900 950 1000 SCHOTTKY FORWARD DROP (mV)
3487 G09
3487 G07
Output Disconnect Voltage Drop (50mA Load)
300 140 120 250 100 80 60 40 20 100 -50 0
Maximum Disconnect Current
VCAP - VPOS = 500mV TA = 25C
200
150
-25
75 0 25 50 TEMPERATURE (C)
100
125
0
2.5
5
7.5
10
12.5
3487 G20
VCAP - VBAT (V)
3487 G11
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LT3487 TYPICAL PERFOR A CE CHARACTERISTICS
Output Disconnect Current Limit
200 VCAP = 15V VBAT = 3.6V VPOS = 0V CURRENT LIMITS (mA) 1200 1150 NEG CHANNEL 1100 1050 1000 950 900 850 100 -50 -25 75 0 25 50 TEMPERATURE (C) 100 125 800 -50 -25 0 50 75 25 TEMPERATURE (C) 100 125 POS CHANNEL
CURRENT LIMITS (mA)
CURRENT LIMIT (mA)
175
150
125
Switch Current Limits vs RUN/SS Voltage (at 55% Duty Cycle)
1000 NEG CHANNEL 3.0 2.5 P0S CHANNEL 600 IRUN/SS (A) 2.0 1.5 1.0 200 0.5
RUN/SS PIN CURRENT (A)
800 CURRENT LIMITS (mA)
400
0
0
250
500 750 1000 RUN/SS (mV)
UVLO Voltage
2.5 300 250 200 150 100 2.1 50
2.4 VRUN/SS (mV)
UVLO (V)
2.3
2.2
2.0 -50
-25
50 25 0 75 TEMPERATURE (C)
UW
3487 G12
Switch Current Limits
1200 1000 800
Switch Current Limits vs Duty Cycle
NEG CHANNEL
P0S CHANNEL 600 400 200 0 0 20 40 60 DUTY CYCLE (%) 80 100
3487 G14
3487 G13
RUN/SS Pin Current in Shutdown
2.0
RUN/SS Pin Current vs VIN in Shutdown
1.5
1.0
0.5
1250
1500
0 -50 -25
0 50 25 75 0 TEMPERATURE (C) 100 125 2 4 6 8 10 VIN (V) 12 14 16
3487 G15
3487 G16
3487 G17
RUN/SS Shutdown Threshold
100
125
0 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
3487 G18
3487 G19
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LT3487 PI FU CTIO S
CAP (Pin 1): Disconnect-PNP Emitter and Positive Schottky Cathode. Acts as an intermediate positive (boost) output. Connect boost output capacitor to this pin. SWP (Pin 2): Switch Pin and Schottky Anode for Positive Channel. Connect boost inductor to this pin. VBAT (Pin 3): Battery Voltage. Connect this pin to the supply voltage for the boost inductor. The disconnect drive current is returned to this pin. The disconnect operates until CAP falls to 1.2V above VBAT. SWN (Pin 4): Switch Pin for Negative (Inverter) Channel. Connect inverter input inductor and flying capacitor here. DN (Pin 5): Anode of Internal Schottky for Inverter. Connect inverter output inductor and flying capacitor here. VIN (Pin 6): Input Supply Pin. VIN is used to power the control circuitry of the LT3487. This pin must be locally bypassed with an X5R or X7R type ceramic capacitor. FBN (Pin 7): Feedback Pin for Inverter. Connect feedback resistor R2 from this pin to VNEG. Choose R2 according to: R2 = - VNEG 25A RUN/SS (Pin 8): Run/Soft-Start Pin. Connect to an opendrain transistor. The transistor must sink 1.4A from RUN/SS. Pull RUN/SS below 100mV to shut down the chip. Connect a capacitor from RUN/SS to ground to program soft-start functionality. The soft-start will slowly bring the boost channel into regulation and then slowly bring up the inverter. RUN/SS must be above 1.6V to allow both channels to reach full current. If soft-start is not required, this pin can be driven with a logic signal, but the RUN/SS voltage must remain below VIN. FBP (Pin 9): Feedback Pin for Boost. Connect boost feedback resistor R1 from FBP to CAP. Choose R1 according to: R1= VPOS - 1.23 25A
Pin voltage = 0V when regulated.
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Pin voltage = 1.23V when regulated. VPOS (Pin 10): Output Pin for Boost Channel. VPOS is the collector of the output disconnect PNP. Connect the boost load to VPOS. Connect capacitor C5 between CAP and VPOS for stability. Exposed Pad (Pin 11): GND. Tie directly to ground plane through multiple vias under the package for optimum thermal performance.
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LT3487 BLOCK DIAGRA
CAP R1 9 FBP 49.2k
A1
VBAT C1
6
VIN VREF 1.23V 1.4A 49.2k RAMP GENERATOR 2MHz OSCILLATOR 160mV 1.25V
+
M1 RUN C6 8 RUN/SS
- +
7 C7 R2
A3
VNEG
DN DN RAMP GENERATOR 5 L3 VNEG C3
3487 BD
Figure 1. Block Diagram
+
-
+
FBN
+
-
-
+
-
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L1 VBAT 2 SWP VCP A2 R X1 S Q Q1 DISCONNECT PNP DP CAP Q3 ANTISAT VBAT VPOS 1 C4 C5 3 10
+
GND
11
VBAT VCN L2 A4 R X2 S Q Q2 C2 SWN 4
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LT3487 APPLICATIO S I FOR ATIO
Operation The LT3487 uses a constant frequency, current mode control scheme to provide excellent line and load regulation. Operation can be best understood by referring to the Block Diagram in Figure 1. At the start of each oscillator cycle, the SR latch X1 is set, which turns on the power switch Q1. A voltage proportional to the switch current is added to a stabilizing ramp and the resulting sum is fed into the positive terminal of the PWM comparator A2. When this voltage exceeds the level at the negative input of A2, the SR latch X1 is reset, turning off the power switch Q1. The level at the negative input of A2 is set by the error amplifier A1, and is simply an amplified version of the difference between the feedback voltage and the reference voltage of 1.23V. In this manner, the error amplifier sets the correct peak current level to keep the output in regulation. If the error amplifier's output increases, more current is delivered to the output; if it decreases, less current is delivered. The second channel is an inverting converter. The basic operation is the same as the positive channel. The SR latch X2 is also set at the start of each oscillator cycle. The power switch Q2 is turned on at the same time as Q1. Q2 turns off based on its own feedback loop, which consists of error amplifier A3 and PWM comparator A4. The reference voltage of this negative channel is ground. Voltage clamps on VCP and VCN (not shown) enforce current limit. Switching waveforms with typical load conditions are shown in Figure 2. The PNP Q3 is used as an output disconnect pass transistor. Q3 disconnects the load from the input during shutdown. The anti-sat driver keeps Q3 at the edge of saturation as
VSWP 20V/DIV ILI 100mA/DIV VSWN 20V/DIV ISWN 100mA/DIV VIN = 3.6V VPOS = 15V, 25mA VNEG = -8V, 50mA 200ns/DIV
3487 F02
Figure 2. Switching Waveforms
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long as CAP is typically 1.2V and worst-case 1.6V (cold) above the VBAT voltage. The drive current for the output disconnect PNP is returned to the VBAT pin. This allows the pass transistor to turn off when the CAP voltage falls to less than 1.2V above VBAT. The VBAT pin allows applications in which the power (inductors L1 and L2) and internal control circuitry (VIN pin) are powered from different sources. Inductor Selection A 10H inductor is recommended for the LT3487 boost channel. The inverting channel can use uncoupled 15H inductors, or coupled 10H inductors. Small size and high efficiency are the major concerns for most LT3487 applications. Inductors with low core losses and small DCR (copper wire resistance) at 2MHz are good choices for LT3487 applications. The inductor DCR should be on the order of half of the switch on-resistance for its channel. Some inductors in this category with small size are listed in Table 1.
Table 1. Recommended Inductors
PART NUMBER DB318C-A997AS100M CDRH3D18-100 CDRH2D18HP-100 CDRH3D23-100 CDRH2D18/HP-150 CDRH3D18-150 CDRH3D23-150 INDUCTANCE DCR (H) () 10 0.18 10 10 10 15 15 15 0.205 0.245 0.117 0.345 0.301 0.191 CURRENT RATING (mA) MANUFACTURER 580 Toko www. tokoam.com Sumida 900 www.sumida.com 850 850 700 750 700
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Capacitor Selection The small size of ceramic capacitors makes them suitable for LT3487 applications. X5R and X7R types of ceramic capacitors are recommended because they retain their capacitance over wider voltage and temperature ranges than other types such as Y5V or Z5U. A 1F input capacitor is sufficient for most LT3487 applications. The output capacitors required for stability depend on the application. For the typical Li-Ion to +15V, -8V application, the positive channel requires a 4.7F output capacitor and the negative channel requires at least 10F of capacitance.
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LT3487 APPLICATIO S I FOR ATIO
MANUFACTURER Taiyo Yuden Murata Kemet PHONE (408) 573-4150 (814) 237-1431 (408) 986-0424
Table 2. Recommended Ceramic Capacitor Manufacturers
URL www.t-yuden.com www.murata.com www.kemet.com
Inrush Current The LT3487 uses internal Schottky diodes. When a supply voltage is abruptly applied to the VIN pin, the voltage difference between VIN and VCAP generates inrush current flowing from the input through the inductor L1 and the internal Schottky diode DP to charge the boost output capacitor C4. For the inverting channel, there is a similar inrush current flowing from the input through the inductor L2 path, charging the flying capacitor C2 and returning through the internal Schottky diode DN. The maximum current the Schottky diodes in the LT3487 can sustain is 2A. The selection of inductor and capacitor values should ensure that the peak inrush current is below 2A. The peak inrush current can be calculated as follows: V - 0.6 - *arctan IP = IN *e * SIN arctan L* r + 1.5 2 *L 1 r = - L * C 4 * L2 =

Table 4. Recommended Schottky Diodes
PART NUMBER PMEG2010AEB FORWARD CURRENT (mA) 1000 FORWARD VOLTAGE DROP (V) 0.51 DIODE CAPACITANCE (pF at 10V) 7.5 MANUFACTURER Philips www.semiconductors. philips.com Central Semiconductor www.centralsemi.com ROHM www.rohm.com Zetex www.zetex.com
CMDSH2-3 RSX051VA-30 ZHCS400
200 500 400
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where L is the inductance, r is the resistance of the inductor and C is the output capacitance. For low DCR inductors, which is usually the case for this application, the peak inrush current can be simplified as follows: V - 0.6 - * 2 IP = IN * e L* Table 3 gives inrush peak currents for some component selections. Note that inrush current is not a concern if the input voltage rises slowly.
Table 3. Inrush Peak Current
VIN (V) 5 5 3.6 3.6 3.6 R () 0.18 0.235 0.18 0.245 0.345 L (H) 10 15 10 10 15 C (F) 4.7 2.2 4.7 4.7 2.2 IP (A)
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1.44 1.06 0.979 0.958 0.704
External Diode Selection As stated previously, the LT3487 has internal Schottky diodes. The Schottky diode, DP, is sufficient for most step-up applications. However, for high current inverter applications, a properly selected external Schottky diode in parallel with DN can improve efficiency. For external diode selection, both forward voltage drop and diode capacitance need to be considered. Schottky diodes rated for higher current usually have lower forward voltage drops and larger capacitance, which can cause significant switching losses at a 2MHz switching frequency. Some recommended Schottky diodes are listed in Table 4.
0.49 0.35 0.425
15 30 18
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LT3487 APPLICATIO S I FOR ATIO
Setting the Output Voltages The LT3487 has an accurate internal feedback resistor that is trimmed to set the feedback currents to 25A for each channel. Only one resistor is needed to set the output voltage for each channel. The output voltage can be set according to the following formulas: V - 1.23 R1= POS 25A R2 = - VNEG 25A
In order to maintain accuracy, high precision resistors are preferred (1% is recommended). Soft-Start The LT3487 has a single soft-start control for both channels. The RUN/SS pin is fed by a 1.4A current source. The soft-start ramp can be programmed by connecting a capacitor from the RUN/SS pin to ground. An open-drain transistor should be used to pull the pin low to shut down the LT3487. Once the transistor stops sinking the 1.4A, the capacitor begins to charge. The chip starts up when the RUN/SS pin charges to 160mV. The VCP node voltage follows the RUN/SS voltage as it continues to ramp up to ensure slow start-up on the positive channel. The VCN node follows the ramp voltage, down a VBE. This ensures that the negative channel starts up after the positive, but still has a slow ramping output to avoid large start-up currents.
VRUN/SS 2V/DIV IIN 1A/DIV VPOS 10V/DIV VNEG 10V/DIV 500s/DIV
3487 F03a
VRUN/SS 2V/DIV IIN 500mA/DIV VPOS 10V/DIV VNEG 10V/DIV 2ms/DIV
3487 F03b
Figure 3a. VRUN/SS, VPOS, VNEG, IIN with No Soft-Start Capacitor
Figure 3b. VRUN/SS, VPOS, VNEG, IIN with a 10nF Soft-Start Capacitor
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Start Sequencing The LT3487 also has internal sequencing circuitry that inhibits the negative channel from operating until the feedback voltage of the boost channel reaches about 1.1V (87% of the final voltage), ensuring that the sum of the two outputs is always positive. There are two ways in which the negative channel may start up, depending on the size of the soft-start capacitor. If there is no soft-start capacitor, or a very small capacitor, then the negative channel will start up when the positive output reaches 87% of its final value. If a large enough soft-start capacitor is used, then the RUN/SS voltage will continue to clamp the negative channel past the point where the positive channel is in regulation. Figure 3 shows the start-up sequencing without soft-start, with a small soft-start capacitor, and a large soft-start capacitor. Output Disconnect The output disconnect uses a PNP transistor with circuitry that varies the base current such that the transistor is consistently at the edge of saturation, thus yielding the best compromise between VCE(SAT) and low quiescent current. To remain stable, this circuit requires a bypass capacitor connected between the VPOS pin and the CAP pin or between the VPOS pin and ground. A ceramic capacitor with a value of at least 0.1F is a good choice. Figure 4 shows that the PNP can support load currents of 50mA with a VCE less than 210mV. The disconnect transistor is current limited to provide a maximum of 155mA in short circuit.
VRUN/SS 2V/DIV IIN 200mA/DIV VPOS 10V/DIV VNEG 10V/DIV 10ms/DIV
3487 F03c
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Figure 3c. VRUN/SS, VPOS, VNEG, IIN with a 100nF Soft-Start Capacitor
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LT3487 APPLICATIO S I FOR ATIO
Choosing a Feedback Node The positive channel feedback resistor, R1, may be connected to the VPOS pin or to the CAP pin (see Figure 5). Regulating the VPOS pin eliminates the output offset resulting from the voltage drop across the output disconnect. However, in the case of a short-circuit fault at the VPOS pin, the LT3487 will switch continuously because the FBP pin is low. While operating in this open-loop condition, the rising voltage at the CAP pin is limited only by the current limit of the output disconnect. Given worst-case parameters this voltage may reach 18V in a Li-Ion application. Care must be taken in high VIN applications when regulating from the VPOS pin. When the short-circuit is removed, the VPOS pin will bounce up to the voltage on the CAP pin, potentially exceeding the programmed output voltage until
300 DISCONNECT SATURATION VOLTAGE (mV) 250 200 150 100 50 0 0 20 40 60 80 DISCONNECT CURRENT (mA) 100
2400 G31
Figure 4. VCE vs I of Output Disconnect
SWN VIN
VBAT
SWP CAP
LT3487 DN FBN RUN/SS GND VPOS VPOS FBP DN FBN
Figure 5. Feedback Connection Using the VPOS and CAP Pins
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the capacitor voltages fall back into regulation. While this is harmless to the LT3487, this should be considered in the context of the external circuitry if short-circuit events are expected. Regulating the CAP pin ensures that the voltage on the VPOS pin never exceeds the set output voltage after a short-circuit event. However, this setup does not compensate for the voltage drop across the output disconnect, resulting in an output voltage that is slightly lower than the voltage set by the feedback resistor. This voltage drop (VDISC) can be accounted for when using the CAP pin as the feedback node by setting the output voltage according to the following formula (using VDISC from Figure 4): R1= VBAT The VBAT pin is a new innovation in the LT3487 that allows output disconnect operation in a wide range of applications. The VBAT pin allows the part to stay on until CAP is less than 1.2V above VBAT. This ensures that the positive bias doesn't fall before the negative bias discharges. In some applications it may be useful to power the inductors from a different source than VIN. In this case, connect VBAT to the source powering the inductors to allow proper operation of the disconnect. For example, in an automotive system there may already be a buck regulator producing 3.3V from a 12V battery. The LT3487 enables the user to power VIN from the 3.3V rail, but power the VBAT pin VPOS + VDISC - 1.23 25A
SWN VIN LT3487 FBP VBAT SWP CAP RUN/SS GND
3487 F05
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VPOS
VPOS
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LT3487 APPLICATIO S I FOR ATIO
and the inductors directly from the battery for higher efficiency. When the part goes into shutdown, the output load is isolated from the 12V source as soon as the CAP node falls to below VBAT plus 1.2V (13.2V in this case). The VBAT pin is also useful in a system using a 2V supply (such as a 2-cell alkaline battery), below the operating range of the LT3487. A boost converter designed for low voltage operation can provide 3.3V for the LT3487 VIN pin, while the inductors and VBAT can still be powered from the 2V supply. In shutdown, the 3.3V supply will turn off, but the output disconnect will still decouple the output load as soon as CAP falls below 3.2V .
VBAT
VNEG
VIN
Figure 6. Recommended Component Placement
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Board Layout Consideration As with all switching regulators, careful attention must be paid to the PCB board layout and component placement. To maximize efficiency, switch rise and fall times are made as short as possible. To prevent electromagnetic interference (EMI) problems, proper layout of the high frequency switching path is essential. The voltage signals of the SWP and SWN pins have rise and fall times of a few ns. Minimize the length and area of all traces connected to the SWP and SWN pins and always use a ground plane under the switching regulator to minimize interplane coupling. Recommended component placement is shown in Figure 6.
CAP
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L1 C2 L3
FBP VPOS
L1
C4 R1 C8 C5
U1 C6
C1 R2 C7
M1
3487 F06
RUN
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LT3487 TYPICAL APPLICATIO U
+15V and -8V Boost and Inverting CCD Bias
L2 15H C2 2.2F C1 1F C7 47pF L1 10H SWN VIN LT3487 DN L3 15H VNEG -8V 90mA C3 22F FBP C4 4.7F FBN R2 324k RUN/SS C6 100nF RUN/SS GND
3487 TA02a
VIN 3V TO 12V
VBAT
SWP CAP R1 549k C5 100nF
VPOS
VPOS 15V 45mA
C1: TAIYO YUDEN EMK212BJ105MG C2: TAIYO YUDEN TMK212BJ225MG C3: TAIYO YUDEN TMK325BJ226MM C4: TAIYO YUDEN TMK316BJ475ML-TR L1: TOKO DB318C-A997AS-100M L2, L3: SUMIDA CDRH2D18/HP-150NC
VPOS Load Step Response
VNEG 20mV/DIV AC-COUPLED
VNEG Load Step Response
VPOS 100mV/DIV AC-COUPLED IPOS 45mA 15mA
-50mA INEG -90mA
VIN = 3.6V
100s/DIV
3487 TA02b
VIN = 3.6V
100s/DIV
3487 TA02c
The positive channel's response is stable, but slightly underdamped. A phase lead capacitor (C8) can be added to provide more ideal phase margin.
VPOS Load Step Response (with Phase Lead Capacitor)
CAP C8 10pF FBP
3487 TA02e
VPOS 100mV/DIV AC-COUPLED R2 549k IPOS 45mA 15mA
VIN = 3.6V
100s/DIV
3487 TA02d
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LT3487 TYPICAL APPLICATIO S
+15V and -8V Low VIN CCD Bias
L2 15H C2 2.2F C1 1F C7 33pF L1 10H
VIN 2.7V TO 5V
L3 15H VNEG -8V 80mA C3 22F
C1: TAIYO YUDEN EMK212BJ105MG C2: TAIYO YUDEN EMK212BJ225MD-TR C3: TAIYO YUDEN TMK325BJ226MM C4: TAIYO YUDEN TMK316BJ475ML-TR L1: TOKO DB318C-A997AS-100M L2, L3: SUMIDA CDRH2D18/HP-150NC
VIN 3V TO 12V C1 1F D1 VNEG -8V 90mA C3 10F
14
U
SWN VIN
VBAT
SWP CAP R1 549k C4 4.7F
LT3487 DN FBP
C8 15pF
C5 100nF
FBN R2 324k RUN/SS C6 100nF RUN/SS GND
3487 TA03
VPOS
VPOS 15V 40mA
+15V and -8V Boost and Charge Pump CCD Bias
L2 15H C2 2.2F L1 10H
SWN VIN
VBAT
SWP CAP R1 549k FBP C4 4.7F
LT3487 DN C7 20pF
C5 100nF
FBN R2 324k RUN/SS C6 100nF RUN/SS GND
3487 TA04
VPOS
VPOS 15V 45mA
C1: TAIYO YUDEN EMK212BJ105MG C2: TAIYO YUDEN TMK212BJ225MG C3: TAIYO YUDEN EMK316BJ106ML C4: TAIYO YUDEN TMK316BJ475ML-TR D1: PHILIPS PMEG2010AEB L1: TOKO DB318C-A997AS-100M L2, L3: SUMIDA CDRH2D18/HP-150NC
3487f
LT3487 PACKAGE DESCRIPTIO U
DD Package 10-Lead Plastic DFN (3mm x 3mm)
(Reference LTC DWG # 05-08-1699)
0.675 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.38 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 6 0.38 0.10 10 3.00 0.10 (4 SIDES) PIN 1 TOP MARK (SEE NOTE 6) 5 0.200 REF 0.75 0.05 2.38 0.10 (2 SIDES) BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 1 1.65 0.10 (2 SIDES)
(DD10) DFN 1103
3.50 0.05 1.65 0.05 2.15 0.05 (2 SIDES)
0.25 0.05 0.50 BSC
0.00 - 0.05
3487f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LT3487 TYPICAL APPLICATIO U
+24V and -16V LCD Bias
L2 22H C2 2.2F C1 1F C7 33pF L1 15H SWN VIN LT3487 DN L3 22H VNEG -16V 26mA C3 22F FBP C4 10F FBN R2 640k RUN/SS C6 100nF RUN/SS GND
3487 TA05
VIN 3V TO 6V
VBAT
SWP CAP C8 15pF R1 931k C5 100nF
VPOS
VPOS 24V 24mA
C1: TAIYO YUDEN EMK212BJ105MG C2: TAIYO YUDEN TMK212BJ225MG C3: TAIYO YUDEN TMK325BJ226MM C4: TAIYO YUDEN TMK316BJ106KL-T L1: SUMIDA CDRH2D18/HP-150NC L2, L3: TOKO D53LC-A915AY-220M
RELATED PARTS
PART NUMBER LT1944/LT1944-1 LT1945 LT1947 LTC(R)3450 LT3463/LT3463A LT3471 LT3472/LT3472A DESCRIPTION Dual Output 350mA/100mA ISW, Constant Off-Time, High Efficiency DC/DC Converter Dual Output, Boost/Inverter, 350mA ISW, Constant Off-Time, High Efficiency DC/DC Converter Triple Output, 3MHz, High Efficiency DC/DC Converter Triple Output, 550kHz, High Efficiency DC/DC Converter Dual Output, Boost/Inverter, 250mA ISW, Constant Off-Time, High Efficiency DC/DC Converter with Integrated Schottkys Dual Output, Boost/Inverter, 1.3A ISW, 1.2MHz, High Efficiency DC/DC Converter Dual Output, Boost/Inverter, 350mA/400mA ISW, 1.2MHz, High Efficiency DC/DC Converter with Integrated Schottkys COMMENTS VIN: 1.2V to 15V, VOUT(MAX) = 34V, IQ = 20A, ISD < 1A, 10-Lead MS Package VIN: 1.2V to 15V, VOUT(MAX) = 34V, IQ = 40A, ISD < 1A, 10-Lead MS Package VIN: 2.6V to 8V, VOUT(MAX) = 34V, IQ = 9.5mA, ISD < 1A, 10-Lead MS Package VIN: 1.4V to 4.6V, VOUT(MAX) = 15V, IQ = 75A, ISD < 2A, DFN Package VIN: 2.2V to 16V, VOUT(MAX) = 40V, IQ = 2.8mA, ISD < 1A, DFN Package VIN: 2.4V to 16V, VOUT(MAX) = 40V, IQ = 2.5mA, ISD < 1A, DFN Package VIN: 2.3V to 15V, VOUT(MAX) = 40V, IQ = 40A, ISD < 1A, DFN Package
3487f
16 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0406 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2006

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